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| CY62148EV30 MoBL(R) 4-Mbit (512K x 8) Static RAM Features * Very high speed: 45 ns -- Wide voltage range: 2.20V - 3.60V * Pin compatible with CY62148DV30 * Ultra low standby power -- Typical standby current: 1 A -- Maximum standby current: 7 A (Industrial) * Ultra low active power * * * * -- Typical active current: 2 mA @ f = 1 MHz Easy memory expansion with CE, and OE features Automatic power down when deselected CMOS for optimum speed and power Available in Pb-free 36-ball VFBGA, 32-pin TSOP II and 32-pin SOIC [1] packages Functional Description [2] The CY62148EV30 is a high performance CMOS static RAM organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH). The eight input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A18). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins. Logic Block Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 CE WE OE INPUT BUFFER ROW DECODER IO0 IO1 SENSE AMPS IO2 IO3 IO4 IO5 IO6 512K x 8 ARRAY COLUMN DECODER POWER DOWN IO7 A13 A14 A15 A16 A17 Notes 1. SOIC package is available only in 55 ns speed bin. 2. For best practice recommendations, refer to the Cypress application note "System Design Guidelines" at http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05576 Rev. *F * 198 Champion Court A18 * San Jose, CA 95134-1709 * 408-943-2600 Revised April 18, 2007 [+] Feedback CY62148EV30 MoBL(R) Pin Configuration [1, 3] 36-Ball VFBGA Pinout Top View NC WE NC A3 A4 A5 A6 A7 A8 IO 0 IO 1 Vcc Vss A18 OE A10 CE A11 A17 A16 A12 A15 A13 IO 2 IO 3 A14 A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 IO0 IO1 IO2 VSS 32-Pin SOIC/TSOP II Pinout Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A0 IO 4 IO 5 VSS VCC IO 6 IO 7 A9 A1 A2 A B C D E F G H VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE IO7 IO6 IO5 IO4 IO3 Product Portfolio Power Dissipation Product Range VCC Range (V) Min CY62148EV30LL VFBGA Industrial TSOP II CY62148EV30LL SOIC Industrial 2.2 3.0 3.6 55 2 2.5 15 20 1 7 2.2 Typ[4] 3.0 Max 3.6 45 Speed (ns) Typ[4] 2 Operating ICC (mA) f = 1 MHz Max 2.5 f = fmax Typ[4] 15 Max 20 Standby ISB2 (A) Typ[4] 1 Max 7 Notes 3. NC pins are not connected on the die. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C. Document #: 38-05576 Rev. *F Page 2 of 12 [+] Feedback CY62148EV30 MoBL(R) Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied............................................... 55C to +125C Supply Voltage to Ground Potential ......................................... -0.3V to VCC(max) + 0.3V DC Voltage Applied to Outputs in High-Z State [5, 6] ........................ -0.3V to VCC(max) + 0.3V DC Input Voltage [5, 6] .....................-0.3V to VCC(max) + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current..................................................... > 200 mA Operating Range Product Range Ambient Temperature VCC [7] 2.2V to 3.6V CY62148EV30 Industrial -40C to +85C Electrical Characteristics (Over the Operating Range) Parameter VOH VOL VIH VIL Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Test Conditions IOH = -0.1 mA IOH = -1.0 mA, VCC > 2.70V IOL = 0.1 mA IOL = 2.1 mA, VCC > 2.70V VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V VCC = 2.2V to 2.7V For VFBGA and TSOP II package For SOIC package VCC = 2.7V to 3.6V For VFBGA and TSOP II package For SOIC package IIX IOZ ICC Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power Down Current -- CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled f = fmax = 1/tRC f = 1 MHz VCC = VCC(max), IOUT = 0 mA, CMOS levels -1 -1 15 2 1 +1 +1 20 2.5 7 -0.3 0.8 -0.3 -1 -1 15 2 1 0.6 [8] +1 +1 20 2.5 7 A A A mA 1.8 2.2 -0.3 45 ns Min Typ[4] 2.0 2.4 0.4 0.4 VCC + 0.3V 1.8 VCC + 0.3V 2.2 0.6 -0.3 0.4 [8] Max 2.0 2.4 0.2 0.4 VCC + 0.3V VCC + 0.3V 55 ns [1] Min Typ[4] Max Unit V V V V V V V V V ISB1 CE > VCC - 0.2V, VIN > VCC - 0.2V, VIN < 0.2V f = fmax (Address and Data Only), f = 0 (OE and WE), VCC = 3.60V ISB2 [9] Automatic CE CE > VCC - 0.2V, Power Down VIN > VCC - 0.2V or VIN < 0.2V, Current -- CMOS f = 0, VCC = 3.60V Inputs 1 7 1 7 A Notes 5. VIL(min) = -2.0V for pulse durations less than 20 ns. 6. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 7. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 8. Under DC conditions the device meets a VIL of 0.8V (for VCC range of 2.7V to 3.6V) and 0.6V (for VCC range of 2.2V to 2.7V). However, in dynamic conditions Input LOW voltage applied to the device must not be higher than 0.6V and 0.4V for the above ranges. This is applicable to SOIC package only. Please refer to AN13470 for details. 9. Only chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 38-05576 Rev. *F Page 3 of 12 [+] Feedback CY62148EV30 MoBL(R) Capacitance (For All packages) [10] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Thermal Resistance [10] Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board VFBGA Package 72 8.86 TSOP II Package 75.13 8.95 SOIC Package 55 22 Unit C/W C/W AC Test Loads and Waveforms VCC OUTPUT R1 VCC 30 pF INCLUDING JIG AND SCOPE R2 GND Rise Time = 1 V/ns 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT OUTPUT Parameters R1 R2 RTH VTH 2.50V 16667 15385 8000 1.20 RTH V 3.0V 1103 1554 645 1.75 Unit V Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR [9] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions VCC = 1.5V, CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Min 1.5 Typ [4] 0.8 Max 7 Unit V A ns ns tCDR [10] tR [11] 0 tRC Data Retention Waveform DATA RETENTION MODE VCC VCC(min) tCDR VDR > 1.5V VCC(min) tR CE Notes 10. Tested initially and after any design or process changes that may affect these parameters. 11. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. Document #: 38-05576 Rev. *F Page 4 of 12 [+] Feedback CY62148EV30 MoBL(R) Switching Characteristics (Over the Operating Range) [12] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE [15] Description 45 ns Min 45 45 10 45 22 5 18 10 18 0 45 45 35 35 0 0 35 25 0 18 10 10 55 40 40 0 0 40 25 0 0 10 5 10 Max Min 55 55 ns [1] Max Unit Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z CE LOW to Low Z [13] [13, 14] ns 55 55 25 20 20 55 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 ns ns OE HIGH to High Z CE HIGH to High Z [13] [13, 14] CE LOW to Power Up CE HIGH to Power Up Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High Z [13, 14] [13] WE HIGH to Low Z Notes 12. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" on page 4. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 15. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document #: 38-05576 Rev. *F Page 5 of 12 [+] Feedback CY62148EV30 MoBL(R) Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [16, 17] tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2 (OE Controlled) [17, 18] ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE DATA OUT VCC SUPPLY CURRENT tPU 50% tLZCE DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE ICC ISB Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [19, 20] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA IO NOTE 21 tHZOE Notes 16. Device is continuously selected. OE, CE = VIL. 17. WE is HIGH for read cycles. 18. Address valid before or similar to CE transition LOW. 19. Data IO is high impedance if OE = VIH. 20. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 21. During this period, the IOs are in output state. Do not apply input signals. tHD DATA VALID Document #: 38-05576 Rev. *F Page 6 of 12 [+] Feedback CY62148EV30 MoBL(R) Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled) [19, 20] tWC ADDRESS tSCE tSA tAW tPWE WE tSD DATA IO DATA VALID tHD tHA CE Write Cycle No. 3 (WE Controlled, OE LOW) [20] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA IO NOTE 21 tHZWE DATA VALID tPWE tHA tHD tLZWE Truth Table CE H L L L WE X H H L OE X L H X High Z Data Out High Z Data in Inputs/Outputs Read Output Disabled Write Mode Deselect/Power down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Document #: 38-05576 Rev. *F Page 7 of 12 [+] Feedback CY62148EV30 MoBL(R) Ordering Information Speed (ns) 45 55 Ordering Code CY62148EV30LL-45BVXI CY62148EV30LL-45ZSXI CY62148EV30LL-55SXI Package Diagram Package Type Operating Range Industrial 51-85149 36-ball Very Fine Pitch Ball Grid Array (Pb-free) 51-85095 32-pin Thin Small Outline Package II (Pb-free) 51-85081 32-pin Small Outline Integrated Circuit (Pb-free) Contact your local Cypress sales representative for availability of these parts. Package Diagrams Figure 1. 36-ball VFBGA (6 x 8 x 1 mm), 51-85149 TOP VIEW BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(36X) 1 2 3 4 5 6 6 5 4 3 2 1 A B C 8.000.10 8.000.10 0.75 5.25 A B C D E 2.625 D E F G H F G H A B 6.000.10 A 1.875 0.75 3.75 B 6.000.10 0.55 MAX. 0.25 C 0.15(4X) 0.210.05 0.10 C 1.00 MAX SEATING PLANE 0.26 MAX. C 51-85149-*C Document #: 38-05576 Rev. *F Page 8 of 12 [+] Feedback CY62148EV30 MoBL(R) Package Diagrams (continued) Figure 2. 32-pin TSOP II, 51-85095 51-85095-** Document #: 38-05576 Rev. *F Page 9 of 12 [+] Feedback CY62148EV30 MoBL(R) Package Diagrams (continued) Figure 3. 32-pin (450 MIL) Molded SOIC, 51-85081 16 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 17 32 0.793[20.142] 0.817[20.751] 0.006[0.152] 0.012[0.304] 0.101[2.565] 0.111[2.819] 0.118[2.997] MAX. 0.004[0.102] 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990] 0.050[1.270] BSC. 0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] SEATING PLANE 51-85081-*B MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05576 Rev. *F Page 10 of 12 (c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62148EV30 MoBL(R) Document History Page Document Title: CY62148EV30 MoBL(R), 4-Mbit (512K x 8) Static RAM Document Number: 38-05576 REV. ** *A ECN NO. 223225 247373 Issue Date See ECN See ECN Orig. of Change AJU SYT New data sheet Changed from Advance Information to Preliminary Moved Product Portfolio to Page 2 Changed VCC stabilization time in footnote #7 from 100 s to 200 s Changed ICCDR from 2.0 A to 2.5 A Changed typo in Data Retention Characteristics (tR) from 100 s to tRC ns Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin Changed tHZOE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45 ns Speed Bin Changed tSCE from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed Bin Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns Speed Bin Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for 45 ns Speed Bin Changed tDOE from 15 to 18 ns for 35 ns Speed Bin Changed Ordering Information to include Pb-Free Packages Changed from Preliminary information to Final Changed the address of Cypress Semiconductor Corporation on Page #1 from "3901 North First Street" to "198 Champion Court" Removed 35ns Speed Bin Removed "L" version of CY62148EV30 Changed ball C3 from DNU to NC. Removed the redundant footnote on DNU. Changed ICC (max) value from 2 mA to 2.5 mA and ICC (Typ) value from 1.5 mA to 2 mA at f=1 MHz Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax Changed ISB1 and ISB2 Typ values from 0.7 A to 1 A and Max values from 2.5 A to 7 A. Changed the AC test load capacitance value from 50pF to 30pF. Changed ICCDR from 2.5 A to 7 A. Added ICCDR typical value. Changed tLZOE from 3 ns to 5 ns Changed tLZCE and tLZWE from 6 ns to 10 ns Changed tHZCE from 22 ns to 18 ns Changed tPWE from 30 ns to 35 ns. Changed tSD from 22 ns to 25 ns. Updated the package diagram 36-pin VFBGA from *B to *C Added 32-pin SOIC package diagram and pin diagram Updated the ordering information table and replaced the Package Name column with Package Diagram. Included Automotive Range in product offering Updated Thermal Resistance table Updated the Ordering Information Added footnote #8 Added VILspec for SOIC package Removed Automotive part and its related information Added footnote #2 related to SOIC package Added footnote #9 related to ISB2 Added AC values for 55 ns Industrial-SOIC range Updated Ordering Information table Description of Change *B 414807 See ECN ZSD *C 464503 See ECN NXR *D *E 833080 890962 See ECN See ECN VKN VKN Document #: 38-05576 Rev. *F Page 11 of 12 [+] Feedback CY62148EV30 MoBL(R) Document Title: CY62148EV30 MoBL(R), 4-Mbit (512K x 8) Static RAM Document Number: 38-05576 REV. *F ECN NO. 987940 Issue Date See ECN Orig. of Change VKN Description of Change Changed VOL spec from 0.4V to 0.2V for SOIC package at IOL = 0.1 mA Changed VIL spec from 0.6V to 0.4V for SOIC package at VCC = 2.2V to 2.7V Updated footnote #8 Made footnote #9 applicable for both ISB2 and ICCDR Document #: 38-05576 Rev. *F Page 12 of 12 [+] Feedback |
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